RSP 2016 Program

Rapid System Prototyping will be part of ESWeek'16, on October, 6-7 2016.
The current final version of the program is presented below.

October, 6th (Thu)

08:50  -  (10 mins) Symposium Opening

Session 1 – Keynote

  • 09:00 - (60 mins) Keynote: Rethinking Memory System Design, Onur Mutlu, ETH Zurich and Carnegie Mellon University

10:00    Coffee Break

Session 2 – Invited Talks: Virtualization and Visualization

  • 10:30 – (30 mins) Invited Paper: Embedded Virtualization for the Design of Secure IoT Applications, Carlos Moratelli, Sergio Johann Filho, Marcelo Neves and Fabiano Hessel – PUCRS
  • 11:00 – (30 mins) Invited Paper: MORPh: Mobile OLED Power Friendly Camera System, Xiang Chen, Jiachen Mao, Jiafei Gao, Kent Nixon, and Yiran Chen – University of Pittsburgh

Session 3 – Embedded Systems for Medical Applications

  • 11:30 – (30 mins) A HW/SW Embedded System for Accelerating Diagnosis of Glaucoma From Eye Fundus Images, Paulo Cezar Dantas Junior, Andrea Sarmento and Adriano Sarmento – Centro de Informatica Universidade Federal de Pernambuco and Clinica Oftalmologica Zona Sul
  • 12:00 – (30 mins) EEGu2: An Embedded Device for Brain/Body Signal Acquisition and Processing, Shen Feng, Mian Tang, Fernando Quivira, Tim Dyson, Filip Cuckov and Gunar Schirner – Northeastern University and University of Massachusetts Boston

12:30    Lunch

Session 4 – Performance and Prototyping with FPGAs

  • 14:00 – (30 mins) Automatic Detection and Elision of Reset Sub-Circuits, Panagiotis Patros and Kenneth Kent – University of New Brunswick
  • 14:30 – (30 mins) Architectural Performance Analysis of FPGA Synthesized LEON Processors, Corentin Damman, Gregory Edison, Fabrice Guet, Eric Noulard, Luca Santinelli and Jerome Hugues – Institute for Space and Aeronautics Engineering (ISAE) and ONERA (The French Aerospace Lab)
  • 15:00 – (30 mins) On-Board Non-Regression Test of HLS Tools Targeting FPGA, Arief Wicaksana, Adrien Prost-Boucle, Olivier Muller, Arif Sasongko and Frédéric Rousseau - Laboratoire TIMA and STEI - Institut Teknologi Bandung

15:30    Coffee Break

Session 5 – Real-time

  • 16:00 – (30 mins) Invited Paper: On platforms for CPS - adaptive, predictable and efficient, Lothar Thiele, Felix Sutton, Romain Jacob, Reto da Forno and Jan Beutel – ETH Zurich
  • 16:30 – (30 mins) Overloads in Compositional Embedded Real-Time Control Systems, Akramul Azim – University of Ontario Institute of Technology
  • 17:00 – (30 mins) Efficient Parallel Multi-Objective Optimization for Real-time Systems Software Design Exploration, Rahma Bouaziz, Laurent Lemarchand, Frank Singhoff, Bechir Zalila and Mohamed Jmaiel - University of Sfax, University of Bretagne Occidentale and Digital Research Center of Sfax
  • 17:30 – (15 mins) Design of an Expandable Real-time Simulation (eRTS) Platform for Multi-level Rapid Prototyping, Ankurkumar Patel, Troy Silloway, Fnu Qinggele and Yong-Kyu Jung – Gannon University and GE Transportation
  • 17:45 – (15 mins) Architecture Exploration of Intelligent Robot System using ROS-compliant FPGA Component, Takeshi Ohkawa, Kazushi Yamashina, Takuya Matsumoto, Kanemitsu Ootsu and Takashi Yokota – Utsunomiya University

18:00    End of day


October, 7th (Fri)

Session 6 – System-on-Chip Prototyping and Simulation

  • 09:00 – (30 mins) Rapid SoC Prototyping Utilizing Quilt Packaging Technology for Modular Functional IC Partitioning, Tian Lu, Jason Kulick, Carlos Ortega, Gary H. Bernstein, Scott Ardisson and Rob Engelhardt – Indiana Integrated Circuits, Manifold Technologies and Plexus Corporation
  • 09:30 – (30 mins) RapidSoC: Short Turnaround Creation of FPGA Based SoCs, Jakob Wenzel and Christian Hochberger - Technische Universität Darmstadt

10:00    Coffee Break

Session 7 – Exploration and Design of Systems

  • 10:30 – (30 mins) Simulation driven insertion of data prefetching instructions for early software-on-SoC optimization, Perrin Njoyah Ntafam, Eric Paire, Alain Clouard and Fréderic Petrot – STMicroelectronics and Univ. Grenoble Alpes, TIMA
  • 11:00 – (30 mins) HAMEX: Heterogeneous Architecture and Memory Exploration framework, Kasra Moazzemi, Roger Chen-Ying Hsieh and Nikil Dutt – University of California Irvine
  • 11:30 – (30 mins) Inter-FPGA Routing Environment for Performance Exploration of Multi-FPGA Systems, Umer Farooq, Roselyne Chotin-Avot, Moazzam Azeem, Maminionja Ravoson and Habib Mehrez - Universite Pierre et Marie Curie (UPMC)
  • 12:00 – (15 mins) Model-driven Design & Synthesis of the SHA-256 Cryptographic Hash Function in ReWire, William Harrison, Adam Procter and Gerard Allwein – University of Missouri and US Naval Research Laboratory
  • 12:15 – (15 mins) Schedulability-Guided Exploration of Multi-core Systems, Rabeh Ayari, Imane Hafnaoui, Giovanni Beltrame and Gabriela Nicolescu - Ecole Polytechnique de Montreal
  • 12:30 – (15 mins) Transforming VHDL Descriptions into Formal Component-based Models, Ayoub Nouri, Rahma Benatitallah, Anca Molnos, Christian Fabre, Frederic Heitzmann and Olivier Debicki – CEA Leti and CEA List

12:45    Symposium Closing