RSP 2026 Program
Note: (s) denotes a 15-minute slot; others are 30 minutes.
09:00 am - 09:15 am Welcome and Opening Remarks
- Georgiy Krylov - University of New Brunswick, Canada - Co-General Chair
- Amer Baghdadi - IMT Atlantique/Lab-STICC, France - Co-General Chair
09:15 am - 10:30 am Keynote - Chair: Amer Baghdadi
- 09:15 am César Fuguet, Ph.D., Researcher at Inria, member of the MADMAX team in the TIMA laboratory, France.
To Full RISC-V Systems and Beyond: Focus on the Memory Hierarchy
10:30 am - 11:00 am Coffee break
11:00 am - 12:30 pm Session 1: Modeling, Simulation and Validation - Session Chair: Felipe Gohring De Magalhaes
- 11:00 am Salim Sama-Mola, Jeremy Nadal, Fatima Hamdar, Charbel Abdel Nour and Amer Baghdadi
A Rapid and Scalable SDR Prototyping Flow for Asynchronous Over-the-Air PHY Validation - 11:30 am Iago Caran Aquino, Lucas Wanner, Sandro Rigo, Tito Mario Burini and Uanderson da Conceição Silva
Modeling Tightly Coupled Accelerators in gem5 - 12:00 pm Dorian Sartori, César Fuguet, Sébastien Jacq, Nicolas Bouron and Frédéric Rousseau
Design, Implementation and Evaluation of a RISC-V IOMMU on gem5
12:30 pm - 01:30 pm Lunch break
01:30 pm - 03:00 pm Session 2: Architectures and Accelerator Integration - Session Chair: Frédéric Rousseau
- 01:30 pm Alireza Azadi, Paul Rigge, Ethan Mahintorabi and Kenneth Kent
Engineering Change Orders for Communicating Processes in High-Level Synthesis - 02:00 pm Adrien Pellé, Lucas Bellier, Théophile Deconche, Stefan Weithoffer, Ali Al Ghouwayel and Amer Baghdadi
Tightly Coupled Acceleration of Compute-Intensive Kernels on RISC-V via In-Pipeline and CV-X-IF Integration - 02:30 pm Jonathas Silveira, Lucas Castro, Sérgio Vargas and Lucas Wanner
Integrating RISC-V with Associative Processing on FPGA
03:00 pm - 03:30 pm Coffee break
03:30 pm - 05:00 pm Session 3: Special Session on RISC-V Extensions, Platforms and Verification - Session Chair: Kenneth Kent
- 03:30 pm Maha Kooli, Thaddée Bricout, Riccardo Alidori, Felix Resch, Tadej Murovic, Pavel Zaykov, Moritz Christamentl and Radu Grosu
Efficient RISC-V Custom Instruction for Near Memory Computing Architecture - 04:00 pm Julio Nunes Avelar, Marcio Aparecido de Godoy Junior, Ana Luiza Paro Costa, Rodolfo Azevedo and Sandro Rigo
Automated OS-Level Verification for RISC-V Softcores: Bridging FPGA and Linux KernelCI - 04:30 pm Ahmet Efe Karagoz, Emir Danisman and Berna Ors
Design of a RISC-V Based SoC with Machine Learning Accelerator Supporting TensorFlow Lite for Microcontrollers
09:15 am - 10:30 am Session 4: Software and Prototyping - Session Chair: Amer Baghdadi
- 09:15 am Mobin Allahdini Hasaroueiyeh, Felipe Gohring de Magalhaes and Tarek Ould-Bachir
Model-Driven Evaluation of LSTM-Based Intrusion Detection for FDI Attacks in Avionics Flight Dynamics - 09:45 am Scott Young, Kenneth Kent and Marius Pirvu
Lightweight Compile-Time Object Reference Tracking for Templated JIT Compilers - 10:15 am (s) Ryo Nishimura, Nao Yoshimura, Hiroshi Oyama and Takuya Azumi
Awkernel+TECS: Component Framework for Rust-based Real-time Operating Systems
10:30 am - 11:00 am Coffee break
11:00 am - 12:30 pm Session 5: Security, Optimizations and Estimation - Session Chair: Georgiy Krylov
- 11:00 am (s) Antoine Bourassa, Felipe Gohring De Magalhaes, Ahmad Shahnejat Bushehri, Rim Zrelli and Gabriela Nicolescu
Polynomial Regression-Based Anomaly Detection on ARINC 429 Using a Custom X-Plane–Derived Dataset - 11:15 am (s) Deesh Patel, Natalie Debiak, Lukash Darewych, Sashwat Sridhar, Nathan Grewal, Wissam Botros, Shawki Areibi and Gary Grewal
A Two-Tier Embedded ML-Based Triage System for Remote Screening and Hospital Prioritization - 11:30 am (s) Robin Gay and Tarek Ould-Bachir
A Scalable, Data-Driven FPGA Stochastic Ising Machine for Combinatorial Optimization - 11:45 am (s) Laleh Akbari and Rolf Drechsler
A Benchmarking Framework for Explainability in Cyber-Physical Systems - 12:00 pm (s) Mustapha Khairan Ghliss, Yehya Nasser, Guy Gogniat and Salam Doumiati
A High-Level Methodology for Cycle-Accurate Power Estimation of Embedded Processors
12:15 pm - 12:30 pm Concluding Remarks
12:30 pm - 01:30 pm Lunch break
Keynote: To Full RISC-V Systems and Beyond: Focus on the Memory Hierarchy
César Fuguet, Ph.D., Researcher at Inria, member of the MADMAX team in the TIMA laboratory, France.
Abstract: The instruction set architecture (ISA) is an essential part of processors. It is the vocabulary that the software uses to indicate the commands (or instructions) to be executed by the processor. Many of our modern computing devices implement proprietary ISAs such as ARM (most smartphones) and x86 (most PCs and servers). However, RISC-V, a free and open ISA created around 2011 by Berkeley, is stirring things up. Its openness enables competition and innovation as it allows both academic and industrial players to implement it without having to pay expensive licenses. This is key to this “new golden age for computer architecture,” as declared by the 2017 Turing Award recipients (John Hennessy and David Patterson), where we need new approaches to keep improving performance and, most importantly, energy efficiency.
This presentation will introduce some of our work where we take advantage of RISC-V to address the performance and energy-efficiency challenges. We show that the openness of RISC-V enables full-stack optimizations; this not only allows us to optimize the processor core's microarchitecture but also system-level aspects (both hardware and software) such as the memory hierarchy and the virtual memory addressing schemes.
Bio: César Fuguet is a researcher at Inria (Institut de Recherche en Informatique et Automatisation) in the TIMA laboratory of the University Grenoble Alpes since November 2024, after spending 9 years as a researcher at CEA (Commissariat à l'Energie Atomique et aux Energies Alternatives). He earned a degree in Computer Systems Engineering from Universidad de Los Andes in Venezuela in 2011 and a PhD in Computer Sciences and Electronics from Université Paris 6 in 2015. His research interests are the hardware design of multi-core, multi-chiplet, heterogeneous architectures, cache hierarchy, and cache coherence with a focus on both performance scalability and energy efficiency. He is co-chair of the Interconnect Task Group in the OpenHW Foundation and an active contributor to open-source hardware projects such as the OpenHW application-class RISC-V CVA6 core.